Analog Synth - Dual ADSR Module

An analog synth should have at least two ADSR modules. Each ADSR module to control:

  1. The VCF (Voltage Controlled Filter)
  2. The VCA (Voltage Controlled Amplifier)

With independent ADSR modules, it is possible to have different Attack, Decay, Sustain and Release envelopes for the filter and amplifier.

Dual Unit Efficiencies

A dual design presents some potential for cost savings, by combining common elements of each. For example, the Gate input and triggering circuitry could be shared by both units. Normally both ADSR units will be triggered simultaneously. Using a shared ADSR triggering circuit also eliminates the need for redundant patch cabling.

One mitigating factor is the potential flexibility of having independently triggered ADSR units, particularly if they can be triggered by non-gate signals.

Gate Input Hysteresis

Schmitt Trigger Output A gate signal is very square as a digital signal. It approaches 5 volts when the note is held on and returns to zero when the note is released. However, if you were to supply an analog signal, perhaps from a LFO, this signal could present triggering issues for the ADSR unit with it's slow rise and fall times.

The solution to this problem is to provide a Schmitt Trigger circuit at the Gate input section. A Schmitt trigger causes a slowly rising signal to cause the circuit's output to snap from a low to a high output in response to the Upper Trip Point (UTP). When the signal slowly falls, the Schmitt trigger circuit will snap from it's high output level to the low level, at the Lower Trip Point (LTP). In this manner, the output of the Schmitt trigger circuit will always have fast rise and fall times, irregardless of it's input.

The picture at right shows a sloppy gate signal rising slowly and falling slowly. A signal like this will not trigger many ADSR designs that use a simple buffer circuit. Normally the UTP is usually set higher than the LTP. In this way, an inut signal that passes the UTP but wanders up and down somewhat will not have the circuit's output going on and off. The graph at right shows that the yellow Schmitt trigger output snaps high (+14.5 volts) when the input signal reaches approximately 2.2 volts. As long as the signal doesn't dip below the LTP of 1 volt in this example, the Schmitt trigger output remains high.

On the falling signal the output snaps low when it drops below the LTP (1 volt). This signal can vary as long as it doesn't go above the UTP (2.2 volts). Using the Schmitt trigger action, a sloppy signal can be cleaned up into a nice proper gate signal.

Design Objectives

With the above considerations in mind, it was time to decide upon design objectives. Was I to go after circuit economy by combining the dual unit with a common gate processing input circuit? Or was I to go after the ultimate in flexibility?

In this design I've decided to pursue flexibility with the following objectives:

  • The ADSR module would be a Dual unit
  • The gate input circuit would provide a Schmitt trigger circuit to square up the Gate signal
  • There will be two gate input circuits (forgoing the economy of sharing a common circuit)
  • There will be a switch to gang the two ADSR units together, to eliminate the need to patch both inputs to the same Gate signal source.

Essentially, this project will be just two halves of the same thing. The exception to this will be the switch to gang the two ADSR units together. A simple approach would be to just switch the 2nd ADSR unit to use the same input signal as the first unit. However, there is the potential problem of the two units not firing simultaneously if the two Schmitt triggers were not exactly identical. With 10% tolerance parts and the very sensitive snapping action of Schmitt trigger circuits, this seems to be a recipe for failure.

A better approach, which will be used, is to switch the Schmitt trigger circuit outputs instead. In this manner, both units will trigger at identical times.

Gate Input Circuit

The Gate input Schmitt trigger circuit The diagram at right, shows the Gate input processing circuit. A pair of LM3900 opamps are used to form a Schmitt trigger. Diode D4 protects against negative going input signals, that may be present in an analog signal like the LFO. The resistors are chosen so that the UTP is around 2 volts and the LTP is approximately 1 volt.

Vref is a signal at half of the +15V supply voltage, to act as a virtual ground for the LM3900s. The LM3900 opamp is a Current Differencing Amplifier (CDA). It was chosen for this design because it is designed for single supply operation. This permits the “low” output for the Schmitt trigger to be a voltage very near zero. A split supply opamp presents a number of difficulties in this regard.

The input verses output plot has been shown previously, in the section about hysteresis. The output of the U2B is near ground when low and approximately a 1.5 volts from Vcc (14.5 volts) when high. This output rises and falls very quickly, which is critical for triggering.

Trigger Circuit

Gate trigger circuit Trigger pulse at the collector of Q1 The Schmitt trigger output feeds into the base of this trigger circuit, consisting of Q1.

The sharp rise of the trigger signal briefly conducts current through capacitor C1, producing a voltage across R5. This causes Q1 to conduct as long as the voltage across R5 is high. The charging time is very brief resulting in a very narrow low going pulse to zero volts.

The graph at right shows in yellow, the input gate signal that causes the Schmitt trigger to activate. From this you can see that the UTP is approximately 2.2 volts.

The collector of Q1 drops from 15 volts to zero and lasts for about 30 micro seconds. This is the signal that will be supplied to the 555 timer trigger input.

ADSR Circuit

The ADSR circuit This is the main meat of the whole module. Shown at left you can see that the collector of Q1 feeds the narrow trigger pulse to the Trigger input of the 555 chip.

One the timer is activated, the output of the 555 timer (pin 3) goes high. The time interval is established by C6 and the Attack circuit attached to this output. The attack circuit is comprised of potentiometer R22, Diode D2 and limiting resistor R2. The main timing components are thus R22 (R2 is small) and C6.

The Decay circuit does not participate at this time due to the reversed biased D1. The cathode of D1 is held near +15V at this time.

The Release branch is supplied by the Schmitt trigger output, which is 14.5 volts during “note on”. The reversed biased diode D5 keeps the Release branch out of the circuit.

While capacitor C6 charges, the voltage level is sensed by the 555 timer by it's pin 6 (THRS). Once C6 charges to approximately 2/3rd of +15V (10V), the 555 returns it's output pin 3 to ground potential. This effectively prevents the Attack circuit from charging C6 any further, since diode D2 is now reversed biased.

At the same time that the 555 output pin 3 is brought low, the DIS pin 7 of the 555 timer is also brought low to discharge the timing capacitor. On the left of R3 is the supply voltage +15V. R20 is the Sustain level potentiometer with it's one leg attached to the 555 timer's discharge pin 7. The wiper arm of R20 then moves from +15V to some level less than or equal to 10 volts, depending upon where the potentiometer is set. Except when the potentiometer is set to maximum sustain, this voltage level will be lower than the threshold voltage of C6 (10V). This permits the charged C6 to flow current through forward biased D1 and potentiometer R21. The Decay pot then determines how quickly C6 discharges to the voltage level held at the wiper arm of R20. Once C6 equalizes within one diode's drop of the sustain level, C6 holds it's charge steady at the sustain level selected.

This continues indefinitely until the Schmitt trigger finally goes low at the falling end of the input gate signal. When the Schmitt trigger output signal goes low, the charge in C6 is now able to flow through forward biased D5 and the Release potentiometer R23 to ground. This causes C6 to be discharged at a rate selected by the Release pot. The capacitor's charge is thus bled away to ground until a new activating gate signal arrives.

Output Buffer Circuit

Output buffer circuit The output buffer circuit must accomplish two things in this module:

  1. It must not leak away the charge held by C6, as it
  2. provides a buffered output of C6's voltage level.

Split supply opamp U3A senses the voltage on C6 and provides a buffered output at pin 2 of the TL072. Requirement 1 eliminated the possibility of the LM3900 being used as an output buffer. It's input would bleed too much current away from C6.

There are two unresolved issues however:

  1. The output voltage level is between 0 and 10 volts, due to the 555 timer operation
  2. The U3A “low” level is between 0.2 and 0.6 volts.

The first problem is solved by placing the output into an output potentiometer. The potential divider provided by the wiper arm selects the output level required (normally about 50% to get a signal with a 5 volt maximum).

The drained voltage level of C6 after it has been charged and discharged is approximately 0.2+0.6 volts above ground. The 0.6 volts is due to diode D5's forward drop. The remaining 0.2 volt drop is due to the minimum V_{CE} in the discharge transistor of the 555 chip.

To compensate for this, transistor Q2 is used in an emitter follower configuration. The signal appearing at Q2's base, will appear at it's emitter leg at a level 0.6 volts lower. When the output level pot R24 is set at 50%, as it would be for normal 5 volt peak output, the remaining 0.2 volts is reduced 50% to 0.1 volts.

Power Circuit

The power section To round out the tour of the ADSR module circuitry, the power section is shown at right. There is nothing remarkable here, except perhaps Vref. Vref is simply voltage divided to be +7.5 volts. It is only used by the LM3900 Schmitt trigger opamps.

The inputs to this module are:

  • +15 volts
  • 0 volts (ground)
  • -15 volts

ADSR Unit One

Click on image for larger view The schematic at left, puts the whole unit into view. You can trace the gate coming into the input at the upper left, going through the LM3900 Schmitt trigger opamps, with it's squared output feeding the Release circuit and the reset input of the 555.

You can also trace the signal going through Q1 to generate that 30 microsecond triggering pulse for the 555 timer. The capacitor and bleed circuits are seen at the lower right.

Using first half of dual 556 The lower middle section illustrates the output buffering to bring the final ADSR signal out to the front panel.

If you choose to use the dual chip (556), use the pin numbers shown at right.

Output Plots

The following graphs represent the plots of one parameter being varied. When a parameter is not being varied, it will assume the following potentiometer setting:

Potentiometer Label %
R22 Attack 90%
R21 Decay 90%
R20 Sustain 50%
R23 Release 90%

The potentiometers are varied according to the following values:

Setting Remarks
5% Low setting (fully counter clockwise)
10%
25%
50% Half setting
75%
90%
95% High setting (fully clockwise)

Attack

Attack control is varied The following plot at right, shows the effect of varying the Attack potentiometer, while the others are held steady.

Decay

Decay control is varied The plot at left shows the effect of varying the Decay control.

Sustain

Sustain control is varied The plot at right shows the effect of varying the Sustain control.

Release

Release control is varied The plot at left shows the effect of varying the Release control.

ADSR Unit Two

Click on the image for higher resolution view The schematic of the second unit is identical to the first, with the exception of part names and pin numbers. The one other feature of this circuit is the switch which allows the user to:

  • Operate each ADSR unit independently
  • Operate both ADSR units from the Gate1 input signal (ganged operation)

556 pinout A DPDT switch is used to choose which pair of gate signals to use. Note that the pair of signals:

  • Schmitt trigger output
  • Trigger pulse for 555 timer

are the ones switched. As noted earlier, don't switch between inputs Gate1 and 2 because the Schmitt trigger action will not occur simultaneously.

Front Panel

Front panel design (reduced) The image at left shows the intended panel design. At the top and middle will be a power LED to indicate that the module has power. Click on image for higher resolution Below the power LED, a small DPDT switch will allow switching between ganged and independent operation.

Two more LEDs appear at the bottom where the Gate and output ADSR jacks are. These will be lit when the unit has been triggered by the Gate signal.

One of the LED drivers is shown at right. The same circuit can be used for the GateB LED. The current drawn by the LED is determined by R1 and the type of LED.

A red LED might draw as much as 13.3 mA in this circuit, where a blue LED may draw as little as 10.5 mA. These are approximate values.

See the table under the heading of "Reading a table of technical data for LEDs" for information about standard LED current consumption by colour.

Checking the Time Constants

The 555 timer reaches it's threshold at \frac{2}{3}V_{cc}. This results in the following time, C and R relationship:

t=1.1CR

The potentiometers affected by charge/discharge time are:

  • Attack (1 Megohm)
  • Decay (1 Megohm)
  • Release (1 Megohm)

The 10 kohm Sustain potentiometer only sets a voltage level.

Armed with the above, we can calculate times for the various settings of the potentiometers:

Setting Resistance Time Comment
0% 1 Megohm 5.17 seconds Maximum time
25% 750 kohm 3.88 seconds
50% 500 kohm 2.59 seconds Half time
75% 250 kohm 1.29 seconds
90% 100 kohm 0.52 seconds
95% 50 kohm 0.256 seconds Near minimum time

Construction

Click on image for closeup The image at right shows the initial wiring of the module. Power lines and the LM3900 section has been wired and tested up to the point of C1/C11. A sine wave test was performed and the outputs confirmed the expected Schmitt trigger action.

Click on image for closeup The next day (left), I wired up the 2N3904 transistor (Q1/Q11) to process the pulse generated. The 2N3904 transistors had a measured Beta of 421, which should be beneficial to the pulse sharpness.

Click on image for closeup The scope trace shown, is the result of a test with a sine wave from a signal generator being fed into the Gate input.

What I was looking for was a solid 30 microsecond pulse, which is clearly visible. Each scope graticule is 5 volts, so you can see a nearly 12 volt drop to ground, and then squarely back up to Vcc. This should be ideal for LM555 triggering.

The signal generator was also varied in amplitude and I continued to see nice solid trigger pulses. Once the input signal dropped below the Schmitt triggering level, the pulse degraded quickly. The threshold where this happens is rather sudden, which is what I expected from the circuit.

Front Panel Build

Click for closeup The most tedious part of each module build is the front panel. I spent a lot of time in OpenOffice's Draw program trying to lay out the panel so that everything was neat and have the parts all fit. The most difficult challenge was getting the potentiometer “numeric dials” to wrap around in a circle around each knob.

The double sided copper had to be cut along with the plexiglass. Then the holes were drilled in the four corners to keep everything in place (with temporary screws).

After all the drilling is completed, a new copy of the front panel is printed on paper to be inserted between the plexiglass and the copper panel. No matter how hard I try, there is always some slippage where the drilled holes moved off target. So a few tweaks were made to the reprinted panel until the printed panel agreed with the drilled holes.

ADSR Unit 1 tested (March 30th, 2012) The photo shows ADSR unit 1's potentiometers in place (on the left), the “independent/ganged” switch, and the input and output jacks. The other potentiometers will be mail ordered.

The LED sticking up out of the PCB was just stuck in some PCB holes. It had been pushed into the power LED hole and come out somehow when I was taking the photos. So it is just lodged there.

On March 30th, unit 1 was wired up and tested without the LEDs installed. The scope trace (left) is dark due to the slow trace rate required and camera used. The photo was Gimp enhanced to bring out the scope trace.

For the scope trace, the ADSR output level was set at “7” while the scope was set to 2 volts per graticule.

Completion Photos

Click on image for closeup The photo at right and below, shows the module prior to installation into the cabinet.

The photo at bottom shows the module installed.

Click on image for closeup Click on image for closeup

synth_dual_adsr.txt · Last modified: 2012/05/16 09:17 by ve3wwg
 
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