Table of Contents

The common emitter design is just an extension of the emitter follower circuit. If you haven't read about the emitter follower yet, I suggest that you do so.

Essentially, the common emitter stage is an emitter follower with a constant current source in the transistor's collector circuit.

A resistor Rc makes a simple constant current source. We know that the voltage at the collector will be the supply voltage minus the voltage dropped across Rc. This of course depends upon the collector current (see Vc calculation shown).

Assuming:

Vcc = +20 volts

we'd want Vc to be approximately half of that (10 volts) so that the signal has maximum wiggle room. With Rc=10k, this means we have about 1 mA flowing through Rc (i.e. 10volts/10kohm = 1 mA).

How did we arrive at Re=1k, you may be wondering? There are a couple of factors to consider:

- Input signal amplitude
- Target gain for this stage

Distortion wise, the most critical aspect is the input signal swing. You will recall that the voltage appearing at the emitter is always the base voltage minus Vbe, which is about 0.6 volts for silicon parts. This circuit uses Re=1k, and we know Ie ~= 1 mA (because Ic=1 mA). Therefore we know the voltage developed across Re will be 1kohm times 1 mA, which is 1 volt.

If the voltage at the base went lower than Vbe (0.6 volts) then the emitter would be unable to be Vbe volts less than that (it can't go negative). So if the input voltage was exactly 0.6 volts, then the emitter would be at zero volts, which is it's absolute lowest voltage.

The bias for the base input voltage has to be 1.6 volts in this case (1 volt at the emitter + 0.6 volts for Vbe). If the base is biased at 1.6 volts, then the most negative amplitude of the input signal is -1 volts. Otherwise clipping and distortion would occur. So if you expect higher amplitude inputs, you'll need to raise the voltage at the emitter, and raise the input base bias voltage also.

The other factor in choosing Rc and Re is the gain of the stage you are designing for. It turns out that the gain for the common emitter stage is easily computed (Kv at left). In our example we can see that the gain is -10 (negative gain just means that the signal is inverted at the output).

If we expect up to a maximum of 1 volt amplitude in the input, with the gain of 10, the output can swing about 1 volt times 10, which is 10 volts at the collector. In reality it will be less than this due to inaccuracies of setting Vc to exactly midway between Vcc and ground, but this gives us an absolute maximum to work with.

To design the bias resistors we just need to know is what voltage to configure the base for. We simply design for the voltage across Re + Vbe. In our example where Vbe=0.6 volts for silicon, this is:

1 volt + 0.6 volts => 1.6 volts

Once you know the voltage needed, you can apply the same process that we used for the emitter follower stage (click here).

The design procedure for the coupling capacitor was also covered in emitter follower stage (click here).

The input impedance of this circuit, when AC coupled with a capacitor (ignoring the capacitor itself) is given by the calculation for Rin at left.

Normally Beta values are high so the input resistance of the transistor can be ignored. For example if the Beta is 100, then the transistor's input resistance is approximately 100k (emitter Re=1k), which is much higher than the bias resistors used. Consequently the approximation of R1||R2 is good enough.

The output impedance is Rc in parallel with the impedance looking into the collector. But if you snip off Rc from the circuit, we have a current source. A current source has very high impedance, and so it can be ignored. This means that the output impedance is simply Rc (or very slightly less than that).

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